1. Field of Invention
This invention relates to a semiconductor memory tester, and a method of testing semiconductor memory. This invention in particular relates to a semiconductor memory tester and a fail information obtaining or storing device for acquiring information when a memory fails, which can be used for a semiconductor memory tester.
2. Description of Related Art
FIG. 1 shows a configuration of a semiconductor memory 40. The semiconductor memory 40 may be a DRAM (Dynamic Random Access Memory). The semiconductor memory 40 comprises a plurality of memory blocks with remedial block 140, which will be referred to as remedial blocks 140. In addition to the main cell area 120, the remedial blocks 140 further comprise a reserve cell area 110 having a spare column 110B and a spare row 110A. The spare column 110B has a plurality of reserve memory cells that will be used to replace failed cells in the column direction. The spare row 110A has a plurality of reserve memory cells to be regressed to failed cells in the row direction.
FIGS. 2(a), 2(b) and 2(c) show the replacement of the failed cells in the reserve cells of the semiconductor memory 40. As shown in FIG. 2(a), the main cell area 120 has a plurality of failed cells 102 which cannot store data correctly. The failed cells 102 shown as xe2x80x9cxxe2x80x9d exist in the column direction. The memory cell line having the failed cell 102 in the column direction is replaced by a line of the spare column 110B as shown in FIG. 2(b).
In this process, the fuse in an address line corresponding to a line having failed cells 102 is cut by laser. The fuses in address lines of the spare column 110B are cut by laser so that the spare column 110B will be selected when an address corresponding to a replaced failed line is accessed. The failed cells 102 are replaced with normal cells as shown in FIG. 2(c). Following this replacement, the semiconductor memory 40 becomes a normal chip having no failed cells.
FIGS. 3(a) to 3(d) show another method of replacing the failed cells with the reserve cells. The main cell area 120 has a plurality of failed cells 102 in the column direction and the spare column 110B also has one failed cell 102 as shown in FIG. 3(a). If the spare column 110B is replaced with a line having a failed cell 102 in its column direction as shown in FIG. 3(b), the replaced line will have one failed cell as shown in FIG. 3(c). To avoid this situation, the line having: failed cells 102 in its column direction, must be replaced with a line from the spare column 110B having no failed cells 102, as shown in FIG. 3(d).
Regarding a semiconductor memory tester, a memory cell function test is usually conducted not only on memory cells in the main cell area 120 but also on memory cells in the reserve cell area 110. The test result is usually stored in a memory of a fail information obtaining or storing device provided in the semiconductor memory tester. Appropriate remedial replacement is undertaken based on the test result.
FIG. 4 shows the process and analysis on failed memory cells in an analyzer and semiconductor tester. Information concerning the failed memory cells in the main cell area 120 and reserve cell area 110 is assumed to have already been tested by the tester and to have been stored in the memory of the fail information obtaining device (not shown).
The analyzer counts failed cells based on the test results in the low addresses for each block and stores the count in a RFCM (row fail count memory). The analyzer also counts failed cells in column addresses and stores it in a CFCM (column fail count memory). The total number of failed cells is also counted and is stored in a TFCM (total fail count memory). This counting process is undertaken by a SCAN operation.
The analyzer then conducts a SEARCH operation. The analyzer analyzes the memory cell lines in the main cell area 120 and reserve cell area 110 for correct replacement, based on the fail counts stored in the RFCM, CFCM and TFCM.
It takes-considerable time to count the failed cells in the above SCAN operation, as the analyzer reads all memory cells stored in the fail information obtaining device when assessing whether or not a certain memory cell is failed. The time necessary for this operation increases as the capacity of the semiconductor memory 40 increases.
To shorten the time necessary for the analysis, a fail information obtaining device 80 is known.
FIG. 5 shows the configuration of the fail information obtaining device 80. The fail information obtaining device 80 comprises an address selector 602, a memory controller 604, a memory 606, a BFM (block fail memory) 612, an SBFM (sub block fail memory) 654, a BFM address selector 608 and an SBFM address selector 610. The memory 606 comprises a plurality of memory elements, each having a predetermined memory capacity.
The address selector 602 selects and outputs an AFM address corresponding to a memory cell in the semiconductor memory 40 under test, based on the address input from a pattern generator (not shown). When a fail signal indicating a memory cell in the semiconductor memory 40 is failed, is input from the logic comparator; the memory controller 604 selects a memory element in the memory 606 to store the fail information, and asserts a fail obtaining signal /STR to be low or xe2x80x9c0xe2x80x9d.
The memory 606 stores as the fail information the logic level H (high) or xe2x80x9c1xe2x80x9d input via the terminal Dn. The data xe2x80x9c1xe2x80x9d is stored to a slot corresponding to the AFM address input via the terminal An, when the fail obtaining signal /STR is xe2x80x9cLxe2x80x9d or low. The fail obtaining signal /STR is input from the memory controller 604 via the terminal /CS.
The BFM address selector 608 selects an address of the remedial block 140 to which the memory cell indicated by the AFM address belongs. This selection is made based on the AFM address input from the address selector 602. The BFM 612 stores as the fail information, the logic H or xe2x80x9c1xe2x80x9d, input via the terminal Dn. The data is stored in a slot corresponding to an address input from the BFM address selector 608 via the terminal An. This occurs when the fail obtaining signal /STR is L, input from the memory controller 604 via the terminal /CS
The SBFM address selector 610 selects an address of a sub block of the remedial block 140 to which the memory cell indicated by the AFM address belongs This selection is made based on the AFM address input from the address selector 602. The SBFM 614 stores as the fail information the logic signal H or xe2x80x9c1xe2x80x9d, input via the terminal Dn. The data xe2x80x9c1xe2x80x9d is stored in a slot corresponding to an address input from the SBFM address selector 610 via the terminal An. This occurs when the fail obtaining signal /STR input from the memory controller 604 via the terminal /CS is xe2x80x9c0xe2x80x9d. There are two different ways for the SBFM address selector 610 to select the address. The SBFM 614 writes the information in a different way for each of the two different methods.
FIG. 6 shows one example of a failed memory cell in the remedial block 140. The remedial block 140 has a plurality of failed cells 102 both in the spare column 110B and spare row 110A.
FIGS. 7(a) and 7(b) show a conventional way for the SBFM 614 to obtain the fail information of the remedial block 140 shown in FIG. 6 In FIG. 7(a), the fail information concerning the spare column 110B and spare row 110A is stored independently of the fail information of the sub block of the main cell area 120. Conversely, in FIG. 7(b), the fail information concerning the spare column 110B and spare row 110A is stored in the same area as the fail information of the sub blocks of the main cell area 120.
In the above fail information obtaining device 80, the time necessary for the analysis of the semiconductor memory 40 can be reduced by using the memory 606, BFM 612 and SBFM 614. In this device, the BFM 612 can indicate the remedial blocks 140 having a failed cell. The SBFM 614 indicates sub blocks having a failed cell in the remedial blocks 140. The analyzer reads the fail information with regard to each memory cell in the memory 606 concerning the indicated sub block, whereas it skips reading out the information of each memory cell in the sub blocks and the remedial blocks 140 when there are no failed memory cells. This skip/SCAN operation can reduce the total time necessary for the analysis.
In the conventional fail information obtaining device 80, it is necessary to provide an extra area for the storage of fail information concerning the sub blocks of the reserve cell area 110. This extra area is in addition to the area for the sub blocks of the main cell area 120 required when the method shown in FIG. 7(a) is adopted, that is, where the fail information is stored in the SBFM 614. In general, the number of sub blocks in the main cell area 120 is 2N and the memory used for the SBFM 614 comprises 2N bits memory area.
In this device, it is necessary to provide an area four times larger than normal in order to store all the fail information. The memory efficiency for this configuration is low because the unusable area shown as the hatched area in FIG. 7(a) is large.
Conversely, when adopting the method shown in FIG. 7(b), unnecessary fail information corresponding to the sub blocks including the failed cells in the reserve cell area 110 will be stored even when the sub blocks in the main cell area 120 have no failed cells. These areas are shown as #0, #1, #2, #3, #4, #8 and #C in FIG. 7(b). Due to this unnecessary storage of fail information in the SBFM 614, the SCAN operation must be conducted over all memory cells in the areas #0 etc. This results in a longer analysis operation.
It is thus the object of the present invention to provide devices and methods for semiconductor memory testing, which reduce the time necessary for the analysis of failed memory cells and which require relatively small memory capacity for storing the fail information. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to one aspect of the present invention, a device (80) for obtaining, or more specifically for storing, fail cell identification information of a semiconductor memory (140) is provided. The memory has blocks with remedial function or remedial blocks. The blocks include a main cell area (120) having memory cells and a reserve cell area (110) having reserve cells for replacing failed memory cells. The fail cell identification information indicates a failed memory cell. The device comprises: an input section (602, 604) for inputting the fail cell identification information; a memory (606) for storing fail cell specification information to specify location of a failed memory cell indicated by the fail cell identification information; a block information memory (612) for storing block specification information indicating a remedial block to which the failed memory cell indicated by the fail cell identification information belongs; a sub block identification information selector (610) for outputting sub block identification information indicating a sub block of the remedial block to which the failed memory cell belongs, indicated by the fail cell identification information; a detector (616) for detecting whether the failed memory cell indicated by the fail cell identification information belongs to the main cell area; and a sub block information memory (614) for storing a sub block specification information specifying the sub block indicated by the sub block identification information when the failed memory cell indicated by the fail cell identification information is detected to belong to the main cell area.
In this configuration, the sub block specification information is not stored in the sub block information memory when the failed memory cell does not belong to the main cell area.
According to another aspect of the present invention, a semiconductor memory tester is provided. The memory (40) has blocks with remedial function or remedial blocks. These blocks have a main cell area (120) that has memory cells and a reserve cell area (110) that has reserve cells for replacing failed memory cells. The tester may employ the aforementioned fail information obtaining device.
The tester comprises: a pattern generator (20) for generating a test pattern to apply to the semiconductor memory, identification information corresponding to the memory cells in the semiconductor memory and expected data to be output therefrom when the memory cells are normal; a waveform shaper (30) for shaping the test pattern signal; a logic comparator (50) for comparing output data output from the semiconductor memory when the shaped test pattern is applied thereto and the expected data; an input section (602, 604) for inputting the identification information as fail cell identification information when the output data and the expected data mismatch; a memory (606) for storing fail cell specification information to specify the memory call indicated by the fail cell identification information; a block information memory (612) for storing block specification information indicating a remedial block to which the failed memory cell indicated by the fail cell identification information belongs; a sub block identification information selector (610) for outputting sub block identification information indicating a sub block of the remedial block to which the failed memory cell belongs, indicated by the fail cell identification information; a detector (616) for detecting whether the failed memory cell indicated by the fail cell identification information belongs to the main cell area; and a sub block information memory (614) for storing a sub block specification information specifying the sub block indicated by the sub block identification information when the failed memory cell indicated by the fail cell identification information is detected to belong to the main cell area.
In this configuration, the sub block specification information is not stored in the sub block information memory when the failed memory cell does not belong to the main cell area.
In the above device or tester, the sub block information memory (614) may store the sub block specification information, utilizing an address bit corresponding to the sub block identification information output. The selector (610) may select as the sub block identification information a plurality of predetermined bits of the fail cell identification information. The detector (616) may detect whether the failed memory cell belongs to the main cell area, based on a predetermined bit of the fail cell identification information.
The detector (616) may comprise a logical AND circuit (622) for calculating logical AND of the predetermined bit of the fail cell identification information and a predetermined logic value. It may be detected whether the failed memory cell indicated by the fail cell identification information belongs to the main cell area (120) or not, based on result of the logical AND operation. The predetermined bit is a bit the value of which becomes constant for addresses inside or outside the main cell area.
According to still another aspect of the present invention, a method of obtaining or storing fail cell identification information of a semiconductor memory (140) is provided. The method comprises: obtaining the fail cell identification information; storing fail cell specification information to specify location of a failed memory cell indicated by the fail cell identification information; storing information indicating a remedial block to which the failed memory cell indicated by the fail cell identification information belongs; obtaining sub block identification information indicating a sub block of the remedial block to which the failed memory cell belongs indicated by the fail cell identification information; detecting whether the failed memory cell indicated by the fail cell identification information belongs to the main cell area or not; and specifying the sub block indicated by the sub block identification information when the failed memory cell indicated by the fail cell identification information is detected to belong to the main cell area.
According to yet another aspect of the present invention, a method for analyzing a semiconductor memory (140) is provided. This method may employ the above method of obtaining or storing fail cell identification information. The method comprises: reading out pre-recorded block specification information indicating a remedial block to which the failed memory cell indicated by the fail cell identification information belongs; analyzing, based on pre-recorded fail memory cell identification information, the reserve memory cell in the remedial block corresponding to the block specification information; reading out, out of pre-recorded sub block specification information indicating a sub block having a remedial block having a main cell area including a failed memory cell therein, a sub block specification information indicating a sub block having a remedial block corresponding to the block specification information, the remedial block having a main cell area including a failed memory cell therein; and analyzing, based on the failed memory cell identification information, the failed memory cell in the main cell area in the sub block corresponding to the read sub block specification information.
This method may further comprise detecting the reserve memory cell in the reserve cell area to replace the failed memory cell in the main cell area, based on the analysis of the reserve memory cell in the reserve cell area and the analysis of the failed memory cell in the main cell area.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.